The present invention relates to detection and control of time or phase differences between electronic signals, such as in delay locked loops.
Delay locked loops (DLLs), particularly of the recirculating type, use clock multiplication and require close alignment between two edges of signals (e.g., clock signals) whose relative phases are being measured or controlled. Digital phase detectors and phase sensitive detectors (PSDs) are known, and are commonly built from exclusive-OR (XOR) logic gates and flip flops (FFs). Other common circuits are phase/frequency detectors, normally made from NAND gate-implemented R-S flip-flops.
Some circuits require very close time alignment between various edges of signals propagating through the circuits. The term xe2x80x9cedgexe2x80x9d is used to describe the transition between two states of a signal. For example, a rising edge is a transition from a low state to a high state, while a falling edge is a transition from a high state to a low state of a signal. Many types of circuits, including data processing and signal processing circuits, use signals which transition between high and low states, sometimes designating two states of a binary system. Clock circuits produce signals which oscillate periodically between a high state and a low state, the periodicity of which defines the frequency of oscillation of the clock.
It is sometimes desired to measure a relative phase difference or time difference between two signals, such as square waves or other signals containing rising and falling edges. Existing methods are typically digital in nature, and include phase detectors and phase/frequency detector circuits, as mentioned briefly above.
One technique for measuring the phase difference between two sine waves involves multiplying the two sine waves. The multiplied signal comprises a DC component that indicates the phase difference. Such solutions work reasonably well for sinusoidal signals, but not so well for other types of signals, such as square waves. Furthermore, these techniques require filtering out the sinusoidal components to obtain the DC signal. Other problems with these techniques include difficulty in determining the actual peaks of the signals, and the possibility of obtaining false locks if the wrong zero of two possible zeros is detected in the process of determining the phase difference.
Other techniques including the use of sample-and-hold (S/H) circuits have been applied to the situation where one signal is a square wave and the other signal is not a square wave, but is a known wave. These techniques require additional processing of the two signals and are not efficient.
Some previous techniques attempted to measure phase differences between two square waves by generating a pulse whose width is equal to the difference in time between the two measured edges. This technique has limitations, especially in fast circuits, as the generated pulse width becomes too narrow. Since pulse rise and fall times are finite, the pulse itself may begin to disappear when the pulse""s rising and falling edges occur close enough to each other so that the pulse is not properly formed.
Foley discloses a technique for detecting both frequency and phase difference (IEEE J. Solid State Circuits, March 2001). Evans discloses a track-and-hold (T/H) circuit as a phase-sensitive detector (IEEE Proceedings, October 1989). Vyroubal (IEEE Trans. Inst. Meas., October 2000) discloses two sinusoidal inputs generating a pulse which must be wider than the combined rise and fall time of the pulse. This approach suffers from the xe2x80x9cdead bandxe2x80x9d problem if the pulse width becomes too small.
Thus, a need exists to measure and detect a phase difference between two square waves and other types of signals. Merely applying the sample-and-hold digital techniques is not very effective in this situation, as it is difficult to determine the individual delays affecting each of the more than one signals being compared, sometimes referred to as xe2x80x9caperture delay.xe2x80x9d Furthermore, for fast switching signals, there is an xe2x80x9caperture windowxe2x80x9d wherein a sample-and-hold switch is neither open nor closed. This situation can lead to errors in the sampled data or to a complete inability to measure very small phase differences, as will be discussed below.
Various embodiments of the present invention are described in more detail below, and solve at least the problems described in the Background section above.
Accordingly, some embodiments of the present invention are directed to a differential sampling circuit, comprising a commutator having at least two inputs that receive a respective first input signal and a second input signal, said commutator having at least a first output and a second output, the first commutator output alternately providing said first and second input signals and the second commutator output alternately providing said second and first input signals, respectively; a sample-and-hold circuit that alternately samples the second commutator output using the first commutator output as a reference, and samples the first commutator output using the second commutator output as a reference, and that provides an interleaved error signal; and a decommutator that receives said interleaved error signal and provides at least two de-interleaved output signals indicative of a time difference between said first and second input signals.
In some aspects, the first and second input signals have matched characteristics, which sometimes may relate said time difference to a corresponding potential difference. The first and second input signals may also comprise digital input signals and/or square waves.
In other aspects, the commutator and the decommutator are complimentary and perform substantially inverse operations. Various embodiments are directed to circuits and systems wherein the decommutator comprises a multiplexer followed by a pair of sample-and-hold circuits each of which receives an output from the multiplexer.
Other embodiments of the above-mentioned circuit comprise a voltage-to-current converter that provides a current signal indicative of said time difference. Said circuits and systems may also comprise an integrator that integrates the current signal and provides an integrated signal. In addition, the circuits and systems may comprise a control circuit that receives the integrated signal and provides a control signal. The control circuit controls any of atidelay, a phase and a frequency of a controlled signal using said control signal according to some embodiments of the present invention. For example, the control circuit may comprise a voltage controlled oscillator.
Yet other embodiments are directed to a method for determining a time difference between at least a first input signal and a second input signal, comprising commutating the first and second input signals to alternately provide the first and second input signals at first and second commutator outputs; alternately sampling the first commutator output using the second commutator output as a reference and sampling the second commutator output using the first commutator output as a reference; generating an interleaved error signal from the first and second commutator outputs; and de-interleaving said error signal to provide at least two de-interleaved output signals indicative of a time difference between the first and second input signals.
The method may further comprise holding the sampled commutator outputs. The method may further comprise converting the de-interleaved output signals from a voltage to a current. According to some aspects, the method further comprises integrating said current to provide an integrated signal and/or generating a control signal from said integrated signal.
Aspects of the invention also comprise controlling a voltage controlled oscillator or a voltage controlled delay element using said control signal.
The embodiment mentioned above may also comprise, in the act of de-interleaving said error signal, multiplexing said error signal and providing a first multiplexed signal and a second multiplexed signal to respective first and second sampling circuits.
Further embodiments are directed to a differential sampling circuit, comprising an input network, said input network comprising a first input line and a second input line, each of said first and second input lines being cross-hard wired to provide a pair of respective first and second input signals; a first sampling circuit and a second sampling circuit, each of said first and second sampling circuits receiving said pair of first and second input signals from the cross-hard wired input lines, said first and second sampling circuits each providing an output voltage; and an error signal, corresponding to a phase difference between said first and second input signals, said error signal representing a potential difference between said first and second sampling circuit outputs. The error signal may correspond to a time delay between said first and second input signals in some embodiments.